1. Field of the Invention The present invention relates to precharge circuits, and more particularly, to a self-timed precharge circuit using a falling edge detector circuit to generate the precharge signal.
2. Description of the Prior Art
Various precharge circuits for memory arrays are known in the prior art. Representative prior art references are described hereinbelow.
In U.S. Pat. No. 4,208,730 issued June 17, 1980 to Dingwall et al entitled PRECHARGE CIRCUIT FOR MEMORY ARRAY, the bit lines of a word organized memory array are precharged to a potential which is substantially equal to the flip points of the memory cells of the array prior to each read and each write operation. This ensures the non-disturbance of the unselected memory cells of the array, provides greater design freedom of the memory array components, and enables the memory array to operate faster and more reliably.
In Japanese Patent No. 56-165983 issued Dec. 19, 1981 to Kiyobumi Ochii entitled SEMICONDUCTOR STORAGE DEVICE, a circuit is provided to enable high speed operation, by starting the precharge through the detection of change in the memory cycle at an address input transition detecting circuit and completing the precharge according to the bit line bit voltage. When any of the address input signals is changed, an input transition detecting circuit detects this and memory cells are turned on in response to the rise of a succeeding synchronizing control signal to start precharging of each bit line. The charging voltage of the lines is detected and when either one output is at 0, a circuit is set to complete the precharge. Thus, the precharge period is not made longer than required and high speed processing can be made for a semiconductor storage device.
In U.S. Pat. No. 4,338,679 issued Jul. 6, 1982 to O'Toole entitled ROW DRIVER CIRCUIT FOR SEMICONDUCTOR MEMORY, a circuit is disclosed for use in a semiconductor integrated circuit memory. The integrated circuit memory includes row lines which serve to activate access transistors for memory cells within the memory circuit. A row decoder circuit receives a plurality of first address bits and produces a drive signal output when the decoder circuit is selected. A transition detector circuit produces a transition signal whenever the state of any of the address bits is changed. A clock decoder receives a plurality of second address bits together with the transition signal to produce a selected clock signal. The combination of the transition signal and the output of the row decoder circuit serves to precharge the gate terminals of the row driver transistor for the row lines. The selected row line receives the active state of the clock signal which causes the gate terminal of the selected row driver transistor to be capacitively coupled to a higher voltage than the clock signal to therefore supply the full clock signal voltage to the row line. The voltage on the row line then activates the access transistors for the memory cells on the row line. This enable a maximum charge to be stored in or read from the memory cell.
In U.S. Pat. No. 4,355,377 issued Oct. 19, 1982 to Sud et al entitled ASYNCHRONOUSLY EQUILLIBRATED ND PRE-CHARGED STATIC RAM, a static random access memory is described wherein fully asynchronous active equilibration and precharging of the RAM's bit lines provides improved memory access time and lower active power dissipation. Each change in the memory's row address is sensed for developing a clock pulse of a controlled duration. The clock pulse is received by a group of equilibrating transistors and a group of precharging transistors which are coupled to the memory's bit lines. When the clock pulse occurs to effect simultaneous equilibration and pre-charging of the bit lines.
In U.S. Pat. No. 3,942,037 issued Mar. 2, 1976 to Mensch, Jr. entitled MOS EDGE SENSING CIRCUIT, an edge sensing circuit is implemented using MOS logic gates. The edge sense circuit detects either a positive transition or a negative transistion of a first input signal depending on the logic level of a second input signal, if an enable signal logical "1" is applied to the edge sense circuit. If the enable signal is at a logical "0", however, a level, rather than a transition, of the input signal is detected.
U.S. Pat. No. 3,909,631 issued Sept. 30, 1975 to Kitagawa entitled PRE-CHARGE VOLTAGE GENERATING SYSTEM relates to a precharge voltage generator for use in an MOS memory matrix device wherein a voltage is generated which is midway between the voltage stored designating a logical 1 and a logical 0. This voltage is constantly variable to track changes in V.sub.DD and V.sub.T during circuit operation to provide the desired midvoltage level and thereby allow accurate recognition of logic levels.
Other references to be noted include U.S. Pat. No. 4,322,825 issued Mar. 30, 1982 to Nagami entitled FLEXIBLE HIDDEN REFRESH MEMORY CIRCUIT and U.S. Pat. No. 4,110,840 issued Aug. 29, 1978 to Abe et al entitled SENSE LINE CHARGING SYSTEM FOR RANDOM ACCESS MEMORY.
The present invention differs from the prior art in that it incorporates the concept of a selftimed precharge circuit using a novel falling edge detector scheme to generate the precharge signal for high-performance CMOS RAMs. The advantages of the proposed circuit compared to other precharge circuits include the fact that by employing such a falling edge detector means, the precharge signal is guaranteed not to be generated before the wordline has reset. Also minimal dc power is dissipated, and the timing skews that would result if a separate timing chain was used are entirely eliminated.